The present invention is directed toward computer memory, and more particularly to determining a resistance level of a memory cell.
Typical semiconductor computer memories are fabricated on semiconductor substrates consisting of arrays of large number of physical memory cells. In general, one bit of binary data is represented as a variation of a physical parameter associated with a memory cell. Commonly used physical parameters include threshold voltage variation of the Metal Oxide Field Effect Transistor (MOSFET) due to the amount of charge stored in a floating gate or a trap layer in non-volatile Electrically Erasable Programmable Read Only Memory (EEPROM), resistance variation of the phase change memory element in Phase-change Random Access Memory (PRAM) or Ovonic Unified Memory (OUM), and charge storage variation in volatile Dynamic Random Access Memory (DRAM).
Increasing the number of bits stored in a single physical semiconductor memory cell is an effective method of lowering the manufacturing cost per bit. Multiple bits of data can also be stored in a single memory cell when variations of the physical parameter can be associated with multiple bit values. Such a multiple bits storage memory cell is commonly known as Multi-Level Cell (MLC). Significant effort in computer memory device and circuit designs is devoted to maximizing the number of bits to be stored in a single physical memory cell. This is particularly true with storage class memory such as popular non-volatile Flash memories commonly used as mass storage device.
The basic requirement for multiple bit storage in a semiconductor memory cell is to have the spectrum of the physical parameter variation to accommodate multiple non-overlapping bands of values. The number of bands required for an n-bit cell is 2n. A 2-bit cell needs 4 bands, a 3-bit cell needs 8 bands and so forth. Thus, the available spectrum of a physical parameter in a semiconductor memory cell is a limiting factor for multiple bit memory storage.